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? semiconductor components industries, llc, 2006 march, 2006 ? rev. 6 1 publication order number: CS8161/d CS8161 12 v, 5.0 v low dropout dual regulator with enable the CS8161 is a 12 v/5.0 v dual output linear regulator. the 12v 5.0% output sources 400 ma and the 5.0 v 2.0% output sources 200 ma. the on board enable function controls the regulator?s two outputs. when the enable pin is low, the regulator is placed in sleep mode. both outputs are disabled and the regulator draws only 200 na of quiescent current. the primary output, v out1 is protected against overvoltage conditions. both outputs are protected against short circuit and thermal runaway conditions. the CS8161 is packaged in a 5 lead to ? 220 with copper tab. the copper tab can be connected to a heat sink if necessary. features ? two regulated outputs ? 12 v 5.0%; 400 ma ? 5.0 v 2.0%; 200 ma ? very low sleep mode current drain 200 na ? fault protection ? reverse battery ( ? 15 v) ? 74 v load dump ? ? 100 v reverse transient ? short circuit ? thermal shutdown these devices are available in pb ? free package(s). specifications herein apply to both standard and pb ? free devices. please see our website at www.onsemi.com for specific pb ? free orderable part numbers, or contact your local on semiconductor sales office or representative. http://onsemi.com pin connections and marking diagram device package shipping ordering information* 50 units/rail CS8161yt5 to ? 220** straight 50 units/rail CS8161ytva5 to ? 220** vertical 50 units/rail CS8161ytha5 to ? 220** horizontal CS8161 awlyww 1 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week to ? 220 five lead t suffix case 314d 1 5 to ? 220 five lead tva suffix case 314k to ? 220 five lead tha suffix case 314a 1 5 1 *consult your local sales representative for so ? 16l package option. **five lead. tab = gnd pin 1. v in 2. v out1 3. gnd 4. enable 5. v out2
CS8161 http://onsemi.com 2 figure 1. block diagram v out2 anti ? saturation and current limit + ? + ? overvoltage shutdown bandgap reference thermal shutdown pre ? regulator v in v out1 enable gnd anti ? saturation and current limit + ? absolute maximum ratings* rating value unit input voltage: operating range overvoltage protection ? 15 to 26 74 v v internal power dissipation internally limited ? junction temperature range ? 40 to +150 c storage temperature range ? 65 to +150 c lead temperature soldering: wave solder (through hole styles only) (note 1) reflow (smd styles only) (note 2) 260 peak 230 peak c c esd (human body model) 2.0 kv 1. 10 second maximum. 2. 60 second maximum above 183 c *the maximum package power dissipation must be observed.
CS8161 http://onsemi.com 3 electrical characteristics for v out: (6.0 v v in 26 v; i out1 = 5.0 ma; i out2 = 5.0 ma; ? 40 c t j +150 c; ? 40 c t a +125 c; unless otherwise specified.) characteristic test conditions min typ max unit primary output stage (v out1 ) output voltage, v out1 13 v v in 26 v, i out1 400 ma 11.4 12.0 12.6 v dropout voltage i out1 = 400 ma ? 0.35 0.6 v line regulation 13 v v in 20 v, 5.0 ma i out < 400 ma ? ? 80 mv load regulation 5.0 ma i out1 400 ma, v in = 14 v ? ? 80 mv quiescent current i out1 100 ma, no load on v out2 i out1 400 ma, no load on v out2 ? ? 8.0 50 12 75 ma ma ripple rejection f = 120 hz, i out = 300 a, v in = 15.0 v dc , 2.0 v rms 42 ? ? db current limit ? 0.40 ? 1.0 a reverse polarity input voltage, dc v out1 ? 0.6 v, 10 load ? ? 30 ? 18 v reverse polarity input voltage, transient 1.0% duty cycle, t = 100 ms, v out ? 6.0 v, 10 load ? ? 80 ? 50 v overvoltage shutdown ? 28 34 45 v short circuit current ? ? ? 700 ma secondary output (v out2 ) output voltage, (v out2 ) 6.0 v v in 26 v, i out2 200 ma 4.90 ? 5.10 v dropout voltage i out2 200 ma ? 0.35 0.60 v line regulation 6.0 v v in 26 v, 1.0 ma i out 200 ma ? ? 50 mv load regulation 1.0 ma i out2 200 ma; v in =14 v ? ? 50 mv quiescent current i out2 = 50 ma i out2 = 200 ma ? ? 5.0 20 10 35 ma ma ripple rejection f = 120 hz; i out = 10 ma, v in = 15 v, 2.0 v rms 42 ? ? db current limit ? 200 ? 600 ma short circuit current ? ? ? 400 ma enable function (enable) input enable threshold v out1 off v out1 on ? 2.00 1.30 1.30 0.80 ? v v input enable current v enable = 5.5 v v enable < 0.8 v 80 ? 10 ? ? 500 10 a a other features sleep mode v enable < 0.4 v ? 0.2 50 a thermal shutdown ? 150 ? 210 c quiescent current in dropout i out1 = 100 ma, i out2 = 50 ma ? ? 60 ma
CS8161 http://onsemi.com 4 package pin description package lead # lead symbol function 5 lead to ? 220 1 v in supply voltage, usually direct from battery. 2 v out1 regulated output 12 v, 400 ma (typ). 3 gnd ground connection. 4 enable cmos compatible input lead; switches outputs on and off. when enable is high v out1 and v out2 are active. 5 v out2 regulated output 5.0 v, 200 ma (typ). typical performance characteristics ? 40 temperature ( c) output current (ma) figure 2. output voltage vs. temperature for v out1 figure 3. line regulation vs. output current for v out1 output current (ma) output current (ma) figure 4. load regulation vs. output current for v out1 figure 5. quiescent current vs. output current for v out1 volt 1 line regulation (mv) load regulation (mv) quiescent current (ma) 0 12.150 12.110 12.070 12.030 11.990 11.950 11.910 11.870 11.830 11.790 11.750 15 100 90 80 70 60 50 40 30 20 10 0 10 5 0 ? 5 ? 10 ? 15 ? 20 ? 25 ? 30 ? 35 ? 40 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 50 0 0 100 150 200 250 300 350 400 450 50 0 50 ? 20 0 20 40 60 80 100 120 140 160 10 5 0 5 10 15 20 25 30 35 40 125 c 25 c ? 40 c v in = 14 v i out1 = 5.0 a v in = 13 ? 26v v in = 14 v v in = 14 v no load on v out2 ? 40 c 125 c 25 c 125 c 25 c ? 40 c
CS8161 http://onsemi.com 5 typical performance characteristics (continued) 0 output current (ma) output current (ma) figure 6. dropout voltage vs. output voltage for v out1 figure 7. quiescent current vs. output current @ dropout for v out1 temperature ( c) output current (ma) figure 8. output voltage vs. temperature for v out2 figure 9. line regulation vs. output current for v out2 150 50 dropout voltage (mv) quiescent current (ma) 3 output voltage load regulation (mv) 25 output current (ma) output current (ma) figure 10. load regulation vs. output current for v out2 figure 11. quiescent current vs. output current for v out2 load regulation (mv) quiescent current (ma) 25 50 8 ? 40 600 5.025 5.020 5.015 5.010 5.005 5.000 4.995 4.990 4.985 4.980 4.975 ? 20 0 20 40 60 80 100 120 140 160 550 500 450 400 350 300 250 200 150 100 50 0 50 500 100 150 200 250 300 350 400 450 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 100 150 200 250 300 350 400 450 50 0 2 1 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 0 50 75 100 125 150 175 200 225 25 0 6 4 2 0 ? 2 ? 4 ? 6 ? 8 ? 10 ? 12 ? 14 ? 16 ? 18 0 50 75 100 125 150 175 200 225 250 25 0 50 75 100 125 150 175 200 225 25 0 45 40 35 30 25 20 15 10 5 0 v in = 11 v ? 40 c 25 c 125 c ? 40 c 125 c 25 c v in = 11 v no load on v out2 v in = 11 v i out = 5.0 ma v in = 6.0 ? 26v 125 c 25 c ? 40 c v in = 14 v 125 c ? 40 c 25 c 125 c 25 c ? 40 c v in = 14 v no load on v out1
CS8161 http://onsemi.com 6 typical performance characteristics (continued) 75 output current (ma) output current (ma) figure 12. dropout voltage vs. output current for v out2 figure 13. quiescent current vs. output current @ dropout for v out2 temperature ( c) v enable (v) figure 14. enable threshold voltage vs. temperature figure 15. enable current vs. enable voltage 60 25 dropout voltage (mv) quiescent current (ma) 100 enable voltage i enable 1.305 1 v enable figure 16. 12 ma enable current vs. enable voltage i enable 0 5 ? 20 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0 25 50 100 125 150 175 200 225 250 55 50 45 40 35 30 25 20 15 10 5 0 0 50 75 100 125 150 175 200 225 250 1.300 1.295 1.290 1.285 ? 40 0 20 40 60 80 100 120 140 80 60 40 20 0 02345 4 3 2 1 0 510152025 v in = 4.0 v no load on v out1 125 c ? 40 c 25 c 25 c 125 c ? 40 c v in = 4.0 v v in = 14 v (1.8500 v, 253.9 na.)
CS8161 http://onsemi.com 7 definition of terms dropout voltage ? the input ? output voltage dif ferential at which the circuit ceases to regulate against further reduction in input voltage. measured when the output voltage has dropped 100 mv from the nominal value obtained at 14 v input, dropout voltage is dependent upon load current and junction temperature. input voltage ? the dc voltage applied to the input terminals with respect to ground. input output differential ? the voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. line regulation ? the change in output voltage for a change in the input voltage. the measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. load regulation ? the change in output voltage for a change in load current at constant chip temperature. long term stability ? output voltage stability under accelerated life ? test conditions after 1000 hours with maximum rated voltage and junction temperature. output noise voltage ? the rms ac voltage at the output, with constant load and no input ripple, measured over a specified frequency range. quiescent current ? the part of the positive input current that does not contribute to the positive load current, i.e., the regulator ground lead current. ripple rejection ? the ratio of the peak ? to ? peak input ripple voltage to the peak ? to ? peak output ripple voltage. temperature stability of v out ? the percentage change in output voltage for a thermal variation from room temperature to either temperature extreme. figure 17. typical circuit waveform 14 v 0 v 0 v 2.0 v 0.8 v v in enable v out1 v out2 60 v 12 v 5.0 v 34 v 12 v 2.4 v 3.0 v 26 v 12 v 0 v 12 v 5.0 v 12 v 14v 0 v load dump low v in line noise, etc. v out1 short circuit v out1 thermal shutdown turn off turn on 2.4 v v out2 short circuit 0 v 0 v 0 v 5.0 v application diagram figure 18. application diagram CS8161 v out1 v out2 enable gnd v in + + * c 1 required if regulator is located far from power supply filter. ** c 2, c 3 required for stability, value may be increased. capacitor must operate at minimum temperature expected. c 1 * 0.1 f c 2 * 22 f c 3 * 22 f tuner display
CS8161 http://onsemi.com 8 application notes since both outputs are controlled by the same enable, the CS8161 is ideal for applications where a sleep mode is required. using the CS8161, a section of circuitry such as a display and nonessential 5.0 v circuits can be shut down under microprocessor control to conserve energy. the example in the applications diagram (figure 18) shows an automotive radio application where the display is powered by the 12 v on v out1 and the t uner ic is powered by the 5.0 v on v out2 . neither output is required unless both the ignition and the radio on/off switch are on. stability considerations the output or compensation capacitor (application diagram c 2 and c 3 ) helps determine three main characteristics of a linear regulator: start ? up delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the cheapest solution, but, if the circuit operates at low temperatures ( ? 25 c to ? 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the values for the output capacitors c 2 and c 3 shown in the test and applications circuit should work for most applications, however it is not necessarily the best solution. to determine acceptable values for c 2 and c 3 for a particular application, start with tantalum capacitors of the recommended value on each output and work towards less expensive alternative parts for each output in turn. step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs on the oscilloscope. a decade box connected in series with the capacitor c 2 will simulate the higher esr of an aluminum capacitor.(leave the decade box outside the chamber, the small resistance added by the longer leads is negligible) step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor c 2 is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. (a smaller capacitor will usually cost less and occupy less board space.) if the capacitor oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next lar ger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real work environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. v ary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitors should be less than 50% of the maximum allowable esr found in step 3 above. once the value for c 2 is determined, repeat the steps to determine the appropriate value for c 3 . calculating power dissipation in a dual output linear regulator the maximum power dissipation for a dual output regulator (figure 19) is p d(max) v in(max) v out1(min) i out1(max) v in(max) v out2(min) i out2(max) v in(max) iq (1) where: v in(max) is the maximum input voltage, v out1(min) is the minimum output voltage from v out1 , v out2(min) is the minimum output voltage from v out2 , i out1(max) is the maximum output current, for the application, i out2(max) is the maximum output current, for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required.
CS8161 http://onsemi.com 9 figure 19. dual output regulator with key performance parameters labeled. smart regulator control features v out1 i out1 v out2 i out2 v in i in i q heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3) where: r jc = the junction ? to ? case thermal resistance, r cs = the case ? to ? heatsink thermal resistance, and r sa = the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
CS8161 http://onsemi.com 10 package dimensions to ? 220 five lead t suffix case 314d ? 04 issue e ? q ? 12345 u k d g a b 5 pl j h l e c m q m 0.356 (0.014) t seating plane ? t ? dim min max min max millimeters inches a 0.572 0.613 14.529 15.570 b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 g 0.067 bsc 1.702 bsc h 0.087 0.112 2.210 2.845 j 0.015 0.025 0.381 0.635 k 0.990 1.045 25.146 26.543 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 u 0.105 0.117 2.667 2.972 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. to ? 220 five lead tva suffix case 314k ? 01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.78 10.54 c 0.160 0.190 4.06 4.83 d 0.027 0.037 0.69 0.94 e 0.045 0.055 1.14 1.40 f 0.530 0.545 13.46 13.84 g 0.067 bsc 1.70 bsc j 0.014 0.022 0.36 0.56 k 0.785 0.800 19.94 20.32 l 0.321 0.337 8.15 8.56 m 0.063 0.078 1.60 1.98 q 0.146 0.156 3.71 3.96 s 0.146 0.196 3.71 4.98 u 0.460 0.475 11.68 12.07 w 55 r 0.271 0.321 6.88 8.15 a u d g b t m 0.356 (0.014) m q 5 pl ? q ? k f j c e ? t ? s l 12345 seating plane r m w
CS8161 http://onsemi.com 11 to ? 220 five lead tha suffix case 314a ? 03 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 0.043 (1.092) maximum. dim a min max min max millimeters 0.572 0.613 14.529 15.570 inches b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 f 0.570 0.585 14.478 14.859 g 0.067 bsc 1.702 bsc j 0.015 0.025 0.381 0.635 k 0.730 0.745 18.542 18.923 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 s 0.210 0.260 5.334 6.604 u 0.468 0.505 11.888 12.827 ? t ? seating plane l s e c f k j optional chamfer 5x d 5x m p m 0.014 (0.356) t g a u b q ? p ? package thermal data parameter to ? 220 five lead unit r jc typical 2.0 c/w r ja typical 50 c/w on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 CS8161/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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